1. Field of the Invention
The present invention is related to a method for fabricating a Dynamic Random Access Memory "DRAM", more particularly to a method for fabricating DRAM device applicable to a highly integrated device.
2. Description of the Related Art
DRAM device is comprised of a cell array part in which memory cells are arranged in a matrix configuration, and a peripheral circuit part for driving the cell array part. In the cell array part, DRAM cells consisting of one transistor and one capacitor are arranged. DRAM cells are connected to word lines and bit lines
On the other hand, the integrity of DRAM device has improved according to the current technical developments in the field of semiconductor device. The improvement in the integrity of the DRAM device incurs reduction in size, i.e. in entire width. In case the width of device is reduced, the distance between the capacitor and the bit line is shortened and the parasitic capacitance therebetween is increased. A signal distortion phenomenon appears thereby causing malfunctions in DRAM device.
Accordingly, there have been proposed various studies to improve the integrity of DRAM device with reduction in width. Among those studies, there is a method to improve the integrity by increasing the number of layers used for DRAM device or by increasing the aspect ratio of the layers. Although this method may contribute to the integrity of DRAM, however it is not desirable since it makes the sequential processes difficult.
Also proposed is another method that the bit line and the capacitor are formed on the opposite sides of the substrate respectively. There is generated little parasitic capacitance between the bit line and the capacitor according to the above structural characteristics. Consequently, this is an effective method for highly integrated device.
FIGS. 1A to 1F are sectional views for showing a conventional DRAM fabricating method that the bit line and the capacitor are formed on the opposite sides of the substrate respectively.
Referring to FIG. 1A, an SOI substrate having a stack structure of a first silicon layer 10, a buried oxide film 11 and a second silicon layer 12 is provided. An isolation film 13 is formed on the second silicon layer 12 so as to be contacted with the buried oxide film 11. A trench 14 is formed on the second silicon layer 12 and a gate oxide film 15 and a conductive layer 16 for a gate are formed on the second silicon layer 12 where the trench 14 is formed and on the isolation film 13 in sequence.
Referring to FIG. 1B, gate electrodes 16a and 16b are formed on both sidewalls of the trench 14 by etching front side of the conductive layer 16. Impurity ions are injected into the second silicon layer 12, thereby forming a first, a second and a third impurity regions 17a, 17b and 17c thereto. Here, the first impurity region 17a and the second impurity region 17b are formed in upper surfaces of the second silicon layer 12 at the both side of the trench 14, and the third impurity region 17c is formed in the silicon layer 12 beneath the bottom of the trench 14. Particularly, the third impurity region 17c is formed so as to be contacted with both the trench 14 and the buried oxide film 11.
Referring to FIG. 1C, a first intermediate insulating layer 18 is formed on the gate oxide film 15 including the gate electrodes 16a and 16b so as to make the trench 14 to be buried. A first contact hole 18a and a second contact hole 18b which expose the first impurity region 17a and the second impurity region 17b are formed on the first intermediate insulating layer 18 according to the photolithography process. Storage electrodes 19 are also formed on the first intermediate insulating layer 18 to be in contact with the first impurity region 17a and the second impurity region 17b through the first contact hole 18a and the second contact hole 18b respectively. A dielectric layer 20 is formed on the storage electrodes 19 and the first intermediate insulating layer 18. A capacitor is constituted by forming a plate electrode 21 on the dielectric layer 20 to cover the storage electrodes 19a and 19b.
Referring to FIG. 1D, a second intermediate insulating layer 22 is formed on the plate electrode 21 and the dielectric layer 20. A third contact hole 22a which exposes the first silicon layer 10, is formed on the second intermediate insulating layer 22 according to the photolithography process. A first conductive layer pattern 24 is formed on the second intermediate insulating layer 22, the first conductive layer pattern 24 includes a first wiring 23 which is in contact with the first silicon layer 10 via the third contact hole 22a. A third intermediate insulating layer 25 is formed on the first conductive layer pattern 24 and the second intermediate insulating layer 22.
FIGS. 1E and 1F are sectional views for showing the above DRAM structure which is rotated by 180 degrees.
Referring to FIG. 1E, an insulating or a conductive dummy substrate 26 is bonded to the third intermediate insulating layer 25. Then, the first silicon layer 10 is removed. The dummy substrate 26 instead of the first silicon layer, serves to maintain the total thickness of DRAM device. A fourth contact hole 11a which exposes the third impurity region 17c, is formed in the buried oxide film 11. A bit line 27 which is in contact with the third impurity region 17c via the fourth contact hole 11a, is formed on the buried oxide film 11.
Referring to FIG. 1F, a fourth intermediate insulating layer 28 is formed on the bite line 27 and the buried oxide layer 11. A fifth contact hole 28a which exposes the first wiring 23, is formed in the fourth intermediate insulating layer 28 according to the photolithography process. A second conductive layer pattern 29 is formed on the fourth intermediate insulating layer 28. The second conductive layer pattern 29 includes a second wiring 29a which is in contact with the first wiring 23.
FIGS. 2A to 2F are sectional views for showing another conventional DRAM fabricating method.
Referring to FIG. 2A, an SOI substrate having a stack structure including a first silicon layer 30, a buried oxide film 31 and a second silicon layer 32 is provided. An isolation film 33 which defines an active region, is formed in the second silicon layer 32 so as to be contacted with the buried oxide film 31. A first trench 34a and a second trench 34b are separately formed on the second silicon layer 32 according to the photolithography process. Herein, the first trench 34a and the second trench 34b are contacted isolation film 33 respectively. A gate oxide film 35 and a conductive layer 36 for a gate are formed on the second silicon layer 32 which includes the first trench 34a and the second trench 34b, and the isolation film 33 in sequence.
Referring to FIG. 2B, gate electrodes 36a through 36d are formed on both sidewalls of the first trench 34a and the second trench 34b by etching the entire conductive layer for gate 36. Impurity ions are injected into the second silicon layer 32, thereby forming a first and a second impurity regions 37a and 37b in the second silicon layer 32 beneath the bottom surfaces of the first trench 34a and the second trench 34b and a third impurity region 37c in the surface of the second silicon layer 32 between the first trench 34a and the second trench 34b. Herein, the first impurity region 37a is formed in contact with the first trench 34a and the buried oxide film 31, and the second impurity region 37b is formed in contact with the second trench 34b and the buried oxide film 31.
Referring to FIG. 2C, a first intermediate insulating layer 38 is formed on the gate oxide film 35 including the gate electrodes 36a through 36b so as to make the trenches to be buried. A first contact hole which exposes the third impurity region 37c, is formed in the first intermediate insulating layer 38 according to the photolithography process. A bit line 39 is formed on the the first intermediate insulating layer 38 to be contacted with the third impurity region 37c through the first contact hole 38a.
Referring to FIG. 2D, a second intermediate insulating layer 40 is formed on the bit line 39 and the first intermediate insulating layer 38. A second contact hole 40a which exposes the first silicon layer 30, is formed on the second intermediate insulating layer 38 according to the photolithography process. A first conductive layer pattern 42 is formed on the second intermediate insulating layer 40, and the first conductive layer pattern 42 includes a first wiring 41 which is in contact with the first silicon layer 30 via the second contact hole 40a. A third intermediate insulating layer 43 is formed on the first conductive layer pattern 42 and the second intermediate insulating layer 40.
FIGS. 2E and 2F are sectional views for showing the above DRAM structure which is rotated by 180 degrees.
Referring to FIG. 2E, an insulating or a conductive dummy substrate 44 is attached to the third intermediate insulating layer 43. Then, the first silicon layer 30 is removed. A third contact hole and a fourth contact hole 31b which expose the first impurity region 37a and the second impurity region 37b, are formed in the buried oxide film 31 according to the photolithography process. Storage electrodes 45a and 45b which are in contact with the first impurity region 37a and the second impurity region 37b via the third and the fourth contact holes 31a and 31b, are formed in the buried oxide film 31.
Referring to FIG. 2F, a dielectric layer 46 is formed on the storage electrodes 45, the buried oxide film 31 and the first wiring 41. A capacitor is constituted by forming a plate electrode 47 to cover the storage electrodes 45a and 45b on the dielectric layer 46. A fourth intermediate insulating layer 48 is formed on the plate electrode 47 and the dielectric layer 46. A fifth contact hole 48a which exposes the first wiring 41, is formed in the fourth intermediate insulating layer 48 according to the photolithography process. A second conductive layer pattern 50 is formed on the fourth intermediate insulating layer 48. The second conductive layer pattern 50 includes a second wiring 49 which is in contact with the first wiring 41 via the fifth contact hole 48a.
The DRAM device fabricated as described above has no parasitic capacitance between the bit line and the capacitor though its entire size may reduce, since the bit line is formed on one side of the second silicon layer and the capacitor is formed on the other side of the second silicon layer i.e. an active layer 32. Therefore DRAM device as constructed above has a high applicability to the integration thereof.
However, it is not easy to perform etching process when the wirings are formed so as to connect a first conductive layer pattern formed in the upper of the second silicon layer and a second conductive layer pattern formed in the bottom of the second silicon layer since it is required to etch at once a plurality of layers including buried oxide film, isolation film and the intermediate insulating layer in a first wiring among the wirings.
Furthermore, the planarization and the photolithography process are affected by the aspect ratio in layers which is not desired from the contact hole forming region during sequential layer forming processes.